Machine Learning Research Intern
IIT Bhubaneswar · Bhubaneswar, India
Worked on Tile Size and Loop Order Selection using Machine Learning for Multi-/Many-Core Architectures, where I developed a Data Dependence Graph (DDG) system that automatically generates randomized, yet representative nested loop structures as comprehensive training data for machine learning models.
- This synthetic loop generator enables ML classifiers to accurately predict optimal tile sizes and loop orders by creating thousands of diverse 2-dimensional loop nests with controlled dependency characteristics, array access patterns, and parallelism properties to improve GPU performance.






